Phase-locked-loop (“PLL”) circuits have been extensively used as a clock distributer in analog electrical systems and communication systems. Some key advantages that a PLL circuit brings to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL circuit enables a periodic signal or a clock signal to be phase-aligned with frequency multiples of a reference clock signal. As the name (i.e., phase locked) implies, an output of the PLL circuit locks onto the incoming reference clock signal and generates a periodic output signal with a frequency equal to the average frequency of the reference clock signal. When the PLL output signal (i.e., the output of the PLL circuit) tracks the reference clock signal such that a difference between a phase of the PLL output signal and a phase of the reference clock signal is constant over time, the PLL circuit is said to be “locked.”
In today's high performance systems operating within increasingly stringent timing constraints, PLL circuits have also been used in digital electronic circuits and/or mixed-signal (i.e., analog and digital) circuits. For example, a PLL circuit that serves as a clock signal distributer of a system-on-chip (SoC) circuit is typically fabricated with the SoC circuit on a single chip. In general, the SoC circuit includes a plurality of sub-system circuits such as, for example, a central processing unit (CPU) circuit, a universal serial bus (USB) circuit, a graphics processing unit (GPU) circuit, a serial AT attachment (SATA) circuit, etc. Each of the sub-system circuits may require a respective clock signal (i.e., a respective frequency) for operations. As such, the PLL circuit of modern SoC circuits typically includes plural sub-PLL circuits, each of which is configured to provide a particular clock signal with a respective frequency to a corresponding sub-system circuit through at least one respective clock tree circuit.
Various issues may arise because of using such an architecture for provisions of plural clock signals. For example, the requirement of plural clock tree circuits may in turn consume additional power and disadvantageously induce undesired noise (e.g., jitter noise). Further, under concern of being interfered by power supply noise, the plural sub-PLL circuits typically use respectively dedicated power supply signals (i.e., instead of using global power supply signals of the SoC circuit), and such sub-PLL circuits can only be deployed away from the sub-system circuits (even away from each sub-PLL circuit's corresponding sub-system circuit). This may accordingly increase complexity in designing a floor plan to lay out the SoC circuit. Thus, existing PLL circuits are not entirely satisfactory.